SLM Engineering Manager

Responsibilities:

· This a manager position and the candidate will need to be able to lead Synopsys Vietnam Solution team which consists of test chip RTL to GDS activities and CAD TFM activities.

· Plan, allocate resources, assign tasks, and direct activities of the team to meet aggressive schedules and achieve milestone criteria.

· Identify and analyze progress gating issues and implement plans, tasks, and solutions to quickly resolve.

· Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of deliverables.

· Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues.

· Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.

Requirements:

·       Have a Bachelor/ Master’s degree in relevant field (Electrical and Electronics or Computer System) with at least 8++ years of experience both in managing and leading a technical team (either on Chip design or CAD methodology domain).

·       Experience in Block floor planning, RTL to gate level netlist generation through synthesis, DFT insertion, placement, clock tree synthesis and route flows, power and static timing analysis and closure, validation of physical design including timing, electrical rules, DRC/LVS, noise, RV checks, formal equivalence verification.

·       Use of industry standard placement and routing CAD tools

·       Fluency in scripting languages (TCL, PERC, Python) and ability to develop tools for ASIC automation.

·       Excellent analytical, problem solving and debugging skills with strong interest in semiconductor technology.

·       Require having at least 3+ years’ experience on managing and leading teams in chip design industries.

·       Individual who consistently look for ways to do things more efficiently while upholding quality. Passionate in solving problems, ability to synthesize data and translate into data driven proposals and decisions.

·       Proficient in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Stay Connected: Join our Talent Community

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

• Degree: Bachelor
• Age: Unlimited
• Working time: Permanent